x63a-c-001-03 1 revision 3.01 graphics s1d13742 s1d13742 mobile graphics engine august 2007 the s1d13742 is a color lcd graphics controller with an embedded 768k byte display buffer. the s1d13742 supports a 8/16-bit intel 80 cpu architecture while providing high performance bandwidth into display memory allowing for fast screen updates. products requiring a rotated display image can take advantage of the swivelview? feature which provides hardware rotation of the display memory transparent to the software application. resolutions supported include 800x480 single buffered and 352x416 double buffered. the s1d13742 uses a double-buffer architecture to prevent any visual tearing during streaming video screen updates. features system block diagram ? embedded 768k byte sram display buffer ? low operating voltage ? 8/16-bit intel 80 interface (used for display or regis- ter data). ? rgb: 8:8:8, 6:6:6, 5:6:5 (8:8:8 will be truncated to 16 or 18 bpp). ? yuv 4:2:2, 4:2:0 (internal yuv to rgb converter stored as 16 or 18 bpp). ? active matrix tft interface - 18/36-bit interface. ? supports resolutions up to 800x480. ? hardware / software power save mode. ? 16/18 bit-per-pixel (bpp) color depths. ? swivelview?: 90, 180, 270 counter-clockwise hardware rotation of display image ? double-buffer available to prevent image tearing during streaming input ? pixel doubling: horizontal and vertical averaging for smooth doubling of a single window ? pixel halving: no limitation on number of windows ? internal programmable pll. ? single mhz clock input: clki. ? general purpose input/output pins. data and cpu control signals 13742 active matrix tft display ? 768k bytes sram s1d137 42 i ncludes: ? pixel doubling ? pixel halving ? swivelview?
revision 3.01 x63a-c-001-03 2 graphics s1d13742 description integrated frame buffer ? embedded 768k byte sram display buffer. cpu interface ? 8/16-bit intel 80 interface (used for display or register data). ? chip select is used to select device. when inactive, any input data/command will be ignored. panel support ? active matrix tft interface. ? 18/36-bit interface. ? supports resolutions up to 800x480. miscellaneous ? internal programmable pll. ? single mhz clock input: clki. ? clki available as clkout (separate clkouten pin associated with output). ? hardware / software power save mode. ? input pin to enable/disable power save mode. ? general purpose input/output pins are available (gpio[7:0]). ? corevdd 1.5 volts and iovdd 1.65 ~ 3.6 volts ? fcbga 121-pin or qfp20 144-pin package digital video ? rgb: 8:8:8, 6:6:6, 5:6:5 (8:8:8 will be truncated to 16 or 18 bpp). ? yuv 4:2:2, 4:2:0 (internal yuv to rgb converter stored as 16 or 18 bpp). display features ? 16/18 bit-per-pixel (bpp) color depths. ? 16 bpp to 18 bpp input data conversion. ? all display writes are handled by window apertures/position for complete or partial display updates. all window coordi- nates are referenced to top left corner of the displayed image (even in a rotated display, the top-left corner is maintained and no host side translation need take place). ? swivelview?: 90, 180, 270 counter-clockwise hardware rotation of display image. all displayed windows can have independent rotation. no additional programming necessary when enabling these modes. ? double-buffer available to prevent image tearing during streaming input. resolutions supported must fit inside 384k bytes (? of total available display buffer). typical resolution of 352x416. ? pixel doubling: horizontal and vertical averaging for smooth doubling of a single window. ? pixel halving: no limitation on number of windows. contact your sales representative fo r these comprehensive design tools ? s1d13742 technical documentation ? cpu independent software utilities ? s1d13742 evaluation boards ? royalty free source level driver code ?seiko epson corporation 2005 - 2007. all rights reserved. information in this document is subject to change without notice. you may download and use this document, but only for your own use in evaluating seiko epson/epson products. you may not modify the document. epson research and development, inc. disclaims any representation that the contents of this docume nt are accurate or current. the programs/technologies described in this document may contain material protected under u.s. and/or international patent laws. epson is a registered trademark of seiko epson corporation. a ll other trademarks are the property of their respective owners. hong kong epson hong kong ltd. 20/f., harbour centre 25 harbour road wanchai, hong kong tel: 2585-4600 fax: 2827-4346 http://www.epson.com.hk/ singapore epson singapore pte ltd 1 harbourfront place #03-02 harbourfront tower one singapore, 098633 tel: (65) 6586-5500 fax: (65) 6271-3182 http://www.epson.com.sg/ europe epson europe electronics gmbh riesstrasse 15 80992 munich, germany tel: 089-14005-0 fax: 089-14005-110 http://www.epson-electronics.de/ japan seiko epson corporation ic international sales group 421-8, hino, hino-shi tokyo 191-8501, japan tel: 042-587-5812 fax: 042-587-5564 http://www.epson.co.jp/ taiwan epson taiwan technology & trading ltd. 14f, no. 7 song ren road taipei 110 tel: 02-8786-6688 fax: 02-8786-6677 http://www.epson.com.tw/ north america epson electronics america, inc. 2580 orchard parkway san jose, ca 95131, usa tel: (408) 922-0200 fax: (408) 922-0238 http://www.eea.epson.com/
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